The present invention relates to a circuit for cutting-off a pulse width modulated (PWM) signal applied to an inverter by an arbitrary width of pulses to protect the inverter (referred to herein as a dead-time generating circuit).
FIG. 1 shows a conventional dead time generating circuit, and FIGS. 2A through 2F are operational timing diagrams of for respective parts in FIG. 1. The dead-time generating circuit shown in FIG. 1 will now be described with reference to the timing diagrams shown in FIGS. 2A through 2F.
An input signal S1 (FIG. 2A) is input to a first input port of a first exclusive OR gate XOR1 and a signal (FIG. 2B) obtained by differentiating the input signal S1 by a capacitor C1 and a resistor R1 is input to a second input port thereof.
Therefore, in first exclusive OR gate XOR1, a value of the differential signal (FIG. 2B) higher than .DELTA.V is recognized as a logic "high." Thus, a signal (an output signal O1) whose logic "high" portion corresponding to .DELTA.t is cut from the original input signal S1 (FIG. 2A) is output, as shown in FIG. 2C.
A signal (FIG. 2D) obtained by inverting the input signal S1 (FIG. 2A) by an inverter INV1 is input to a first input port of a second exclusive OR gate XOR2 and a signal (FIG. 2E) obtained by differentiating the inverted signal (FIG. 2D) by a capacitor C2 and a resistor R2 is input to a second input port thereof.
Like in first exclusive OR gate XOR 1, in second exclusive OR gate XOR2, a value of the differential signal (FIG. 2E) higher than .DELTA.V is recognized as a logic "high." Thus, a signal (an output signal O2) whose logic "high" portion corresponding to .DELTA.t is cut from the original inverted signal (FIG. 2D) is output, as shown in FIG. 2F.
As described above, in the conventional dead-time generating circuit, exclusive OR operations are executed with respect to an input signal and the signal differentiated by a capacitor and a resistor to cut the forehead of the logic "high" portion of the input signal. However, since the value of .DELTA.t is changed depending on the change in capacitance or resistance value due to ambient temperature or humidity, it is difficult to cut the logic "high" portion of the input signal with a constant interval. Also, the value of .DELTA.t can be only changed by replacing the capacitor or resistor.